Multilayer circuit boards and integrated circuits are well known in the art. Currently, printed circuit boards can contain 8 metal layers and are typically designated Metal 1 through Metal 8. Each layer includes conductive material. To simplify interconnect design, typically, the conductive material in each layer runs in a specific lengthwise direction parallel to the length or width of the substrate (e.g., PC board or chip die) where the direction between successive layers alternates in direction. For instance, Metal 1 may include conductive material which runs in the xe2x80x9cxxe2x80x9d direction, while Metal 2 includes conductive material which runs only in the xe2x80x9cyxe2x80x9d direction and Metal 3 includes conductive material which runs only in the xe2x80x9cxxe2x80x9d direction. Typically, various layers in a printed circuit board or the wiring layer of an integrated circuit are electrically connected to one another by boring or etching a hole between the layers which are to be connected and filling all or a portion of that hole with a metal conductor which connects the conductive material (i.e., wiring) of the first layer with the conductive material of the second layer.
For example, a hole may be drilled in Metal 2 and a connection may be made between the conductive material in Metal 2 and the conductive material in Metal 1. Multilayer boards are well known in the art and connections between various layers of multilevel boards are described in detail in U.S. Pat. No. 5,666,722 issued to Tamm et al. on Sep. 16, 1997 and U.S. Pat. No. 6,004,619 issued to Dippon et al. on Dec. 21, 1999, both of which are incorporated in their entirety herein and are assigned to the assignee of the present patent application. Typically, on each connected layer, a contact pad is included to ensure that the hole drilled between the layers contacts the conductive material on each of the layers. Such contact pads are usually wider than the minimum wiring width in part, so that when the through hole is formed, sufficient material surrounds the hole so that the wiring is not broken and sufficient area is provided to join or bond the metal conductor (or xe2x80x9cjumperxe2x80x9d) to the interconnecting layer.
The present invention is directed to a system and method which identifies the location of contact pads on interconnect layers of printed circuit boards or metal layers of integrated circuits. The invention groups the conductive surfaces into rectangular areas and applies a mask to the identified rectangular areas by aligning a corner of the mask with the corresponding corner of the rectangular area. Once aligned, the remaining corners of the mask are checked to see whether there is an underlying conductive material present at all corners thereby identifying a suitable location for a contact pad. A further embodiment of the invention includes an alignment of alternate corners of the mask with the corresponding corner of the rectangular area if previous attempts to identify a contact pad were unsuccessful.